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r2045s/d 4-wire serial interface real time clock module no.ea-113-0603 1 outline the r2045s/d is a real-time clock module, built in cmos real-time clock ic and crystal oscillator, connected to the cpu by four signal lines, ce, sclk, si, and so, and configured to perform serial transmission of time and calendar data to the cpu. the oscillation frequency is adjusted to high precision (0 5ppm: 15sec. per month at 25 c) the periodic interrupt circuit is configured to genera te interrupt signals with six selectable interrupts ranging from 0.5 seconds to 1 month. the 2 alarm interrupt circuits generate interrupt si gnals at preset times. as the oscillation circuit is driven under constant voltage, fluctuation of the oscillator frequency due to supply voltage is small, and the time keeping current is small (typ. 0.48 a at 3v). the oscillation halt sensing circuit can be used to judge the validity of internal data in such ev ents as power-on; the supply voltage monitoring circuit is configured to record a drop in supply voltage below tw o selectable supply voltage monitoring threshold settings. the 32-khz clock output function (n-c hannel open drain output) is intended to output sub-clock pulses for the external microcomputer. the oscillation adjustment circuit is intended to adjust time by correcting deviations in the oscillation frequency of the crystal oscillator. features ? built in 32.768khz crystal unit, the oscillation frequency is adjusted to high precision (0 5ppm: at 25 c) ? time keeping voltage 1.15v to 5.5v ? super low power consumption 0.48 a typ (1.2 a max) at v dd =3v ? four signal lines (ce, sclk, si, and so) required for connection to the cpu. ? time counters (counting hours, minutes, and second s) and calendar counters (c ounting years, months, days, and weeks) (in bcd format) ? interrupt circuit configured to generate interrupt si gnals (with interrupts ranging from 0.5 seconds to 1 month) to the cpu and provided with an interrupt flag and an interrupt halt ? 2 alarm interrupt circuits (alarm_w for week, hour, and minute alarm settings and alarm_d for hour and minute alarm settings) ? 32768hz clock output pin (n-channel open drain output) ? with power-on flag to prove that the power supply starts from 0v ? with oscillation halt sensing flag to ju dge the validity of internal data ? supply voltage monitoring circuit with two supply voltage monitoring threshold settings ? automatic identification of leap years up to the year 2099 ? selectable 12-hour and 24-hour mode settings ? oscillation adjustment circuit for correcting temp erature frequency deviation or offset deviation ? cmos process ? two types of package, sop14(10.1x7 .4x3.1) or son22(6.1x5.0x1.3)
r2045s/d 2 pin configuration sclk so vss vdd n.c. 1 2 3 4 5 6 7 9 top view r2045s (sop14) 32kout 10 8 si 11 12 13 14 n.c. vpp n.c. n.c. ce n.c. intr sclk so vss vdd ce 1 2 3 4 5 6 7 9 top view R2045D (son22) 32kout 10 8 si 11 15 16 14 vpp n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. 18 19 17 21 22 20 intr block diagram 32khz output control osc comparator_d alarm_d register (min,hour) address decoder address register voltage detect div time counter (sec,min,hour,week,day,month,year) shift register i/o control 32kout interrupt control sclk divider correc -tion vdd vss comparator_w alarm_w register (min,hour, week) ce osc detect si test circuit so vpp intr
r2045s/d 3 pin description symbol item description ce chip enable input the ce pin is used for interfacing with the cpu. should be held high to allow access to the cpu. incorporat es a pull-down resistor. should be held low or open when the cpu is powered off. a llows a maximum input voltage of 5.5v regardless of supply voltage. sclk serial clock input the sclk pin is used to input cl ock pulses synchronizing the input and output of data to and from the si and so pins. allows a maximum input voltage of 5.5v regardless of supply voltage. si serial input the si pin is used to input data intended for writing in synchronization with the sclk pin. cmos input. allows a maximum input voltage of 5.5v regardless of supply voltage. so serial output the so pin is used to output data intended for reading in synchronization with the sclk pin. cmos output. intr interrupt output the intr pin is used to output alarm interrupt (alarm_w) and alarm interrupt (alarm_d) and output periodic in terrupt signals to the cpu signals. disabled at power-on from 0v. n-channel open drain output. allows a maximum pull-up voltage of 5.5v regardless of supply voltage. 32kout 32khz clock output the 32kout pin is used to output 32.7 68-khz clock pulses. and controlled by resister setting. when vdd power-on from 0v, this output is enabled. the pin is n-channel open drain output. allows a maximum pull-up voltage of 5.5v regardless of supply voltage. vdd positive power supply input the vdd pin is connected to the power supply. vss negative power supply input the vss pin is grounded. vpp test input this pin is power pin for testi ng in the factory. pleas e don?t connect to any other pins. n.c. no connection these pins are not connected to internal ic chip. in R2045D (son22), n.c. pins from 14 pin to 22 pin are connected together internally. never connect these pins to any lines, or connect to vdd or vss. and never connect different voltage level lines each other.
r2045s/d 4 absolute maximum ratings (v ss =0v) symbol item pin name and condition description unit v dd supply voltage vdd -0.3 to +6.5 v input voltage 1 ce, sclk, si -0.3 to +6.5 v i input voltage 2 vpp -0.3 to v dd +0.3 v output voltage 1 so -0.3 to v dd +0.3 v o output voltage 2 intr , 32kout -0.3 to +6.5 v p d power dissipation topt=25 c 300 mw topt operating temperature -40 to +85 c tstg storage temperature -55 to +125 c recommended operating condition (v ss =0v, topt=-40 to +85 c) symbol item pin name and condition min. typ. max . unit v access supply voltage vdd power supply voltage for interfacing with cpu 1.7 5.5 v v clk time keeping voltage 1.15 5.5 v v pup pull-up voltage intr 5.5 v frequency characteristics (v ss =0v) symbol item condition min. typ. max. unit ? f/f0 frequency deviation topt=25 c, v dd =3v -5 0 +5 ppm fv frequency voltage characteristics topt=25 c, v dd =2.0v to 5.5v -1 +1 ppm top frequency temperature characteristics topt=-20 c to +70 c 25 c as standard -120 +10 ppm tsta oscillation start-up time topt=25 c, v dd =2v +1 sec fa aging topt=25 c, v dd =3v, first year -5 +5 ppm
r2045s/d 5 dc electrical characteristics unless otherwise specified: v ss =0v,v dd =3v,topt=-40 to +85 c symbol item pin name condition min. typ. max. unit v ih ?h? input voltage 0.8x v dd 5.5 v il ?l? input voltage ce, sclk, si v dd =1.7 to 5.5v -0.3 0.2x v dd v i oh ?h? output current so v oh =v dd -0.5v -0.5 ma i ol1 intr 2.0 i ol2 ?l? output current so, 32kout v ol =0.4v 0.5 ma i il input leakage current sclk, si v i =5.5v or v ss v dd =5.5v -1.0 1.0 a r dnce pull-down resistance ce 40 120 400 k ? i oz1 so vo=5.5v or v ss vdd=5.5v -1.0 1.0 i oz2 output off-state leakage current intr , 32kout vo=5.5v -1.0 1.0 a i dd1 vdd v dd =3v, ce, sclk, si, so, intr , 32kout =v ss 32kout disabled 0.48 1.20 i dd2 vdd v dd =5v, ce, sclk, si, so, intr , 32kout =v ss 32kout disabled 0.60 1.80 i dd3 time keeping current vdd v dd =3v, ce, sclk, si, so, intr , 32kout =v ss 32kout enabled 0.65 2.00 a v deth supply voltage monitoring voltage (?h?) vdd topt=-30 to +70 c 1.90 2.10 2.30 v v detl supply voltage monitoring voltage (?l?) vdd topt=-30 to +70 c 1.15 1.30 1.45 v
r2045s/d 6 ac electrical characteristics unless otherwise specified: v ss =0v,topt=-40 to +85 c input / output condition: v ih =0.8xv dd ,v il =0.2xv dd ,v oh =0.8xv dd ,v ol =0.2xv dd ,cl=50pf v dd 1.7v symbol item condi- tions min. typ. max. unit t ces ce set-up time 400 ns t ceh ce hold time 400 ns t cr ce recovery time 62 s f sclk sclk clock frequency 1.0 mhz t ckh sclk clock high time 400 ns t ckl sclk clock low time 400 ns t cks sclk set-up time 200 ns t rd data output delay time 300 ns t rz data output floating time 300 ns t cez data output delay time after falling of ce 300 ns t ds input data set-up time 200 ns t dh input data hold time 200 ns scl k t ces si ce t rd t ckl t cez t ds t dh t rd t ceh t ckh t cks t cr t rz so *) for reading/writing timing, see ?p.26 ? considerations in reading and writing time data under special condition?.
r2045s/d 7 package dimensions ? r2045s (sop14) #14 #7 #1 #8 5.0 0.2 10.1 0.2 7.4 0.2 0.6 0.25 0.15 +0.1/-0.05 0 -10 0.35 +0.1/-0.05 1.27 0.1 1.2 0.1 +0.1/-0.05 3.1 +0.0/-0.05 0.1 1.24typ. ? R2045D (son22) a 6.1 0.2 #22 #14 #1 #11 4.7 0.2 5.0 0.2 0.2 0.1 0.5 0.1 0.1 0.125 +0.1/-0.05 1.3 0.1 #1 #11 #22 #14 0.3 0.1 0.43 0.43 0.05 a b a ? b b 0.2 0.2 0.1 0.3 0.65 a ? 0.3 0.2 0.55typ.
r2045s/d 8 general description ? interface with cpu the r2045s/d is connected to the cpu by four signal lines ce (chip enable), sclk (serial clock), si (serial input), and so (serial output), through which it reads and writes data from and to the cpu. the cpu can be accessed when the ce pin is held high. access cloc k pulses have a maximum frequency of 1 mhz allowing high-speed data transfer to the cpu. ? clock and calendar function the r2045s/d reads and writes time data from and to t he cpu in units ranging from seconds to the last two digits of the calendar year. the calendar year will auto matically be identified as a leap year when its last two digits are a multiple of 4. consequently, leap years up to the year 2099 can automatic ally be identified as such. ? alarm function the r2045s/d incorporates the alarm interrupt circuit configured to generate interrupt signals to the cpu at preset times. the alarm interrupt circuit allows two ty pes of alarm settings specified by the alarm_w registers and the alarm_d registers. the al arm_w registers allow week, hour, and minute alarm settings including combinations of multiple day-of-week settings su ch as "monday, wednesday, and friday" and "saturday and sunday". the alarm_d registers allow hour and mi nute alarm settings. the alarm_w outputs from intr pin, and the alarm_d outputs also from intr pin. each alarm function can be checked from the cpu by using a polling function. high-precision oscillation adjustment function to correct deviations in the oscillati on frequency of the crysta l oscillator, the oscillation adjustment circuit is configured to allow correction of a time count gain or loss (up to 1.5 ppm at 25 c) from the cpu within a maximum range of approximately + 189 ppm in increments of approximately 3 ppm. such oscillation frequency adjustment in each system has the following advantages: * corrects seasonal frequency deviations through seasonal oscillation adjustment. * allows timekeeping with higher precision particular ly with a temperature sensing function out of rtc, through oscillation adjustment in tune with temperature fluctuations. ? oscillation halt sensing flag, power-on reset flag, and supply voltage monitoring function the r2045s/d incorporates an oscillation halt sensing ci rcuit equipped with internal registers configured to record any past oscillation halt. power-on reset flag is set to ?1? when r2045s/d is powered on from 0v. as such, the oscillation halt sensing flag and power-on re set flag are useful for judging the validity of time data. the r2045s/d also incorporates a supply voltage monitoring circuit equipped with internal registers configured to record any drop in supply voltage below a certain threshold value. supply voltage monitoring threshold settings can be selected between 2.1 and 1.3 vo lts through internal register settings. the oscillation halt sensing circuit is configured to confirm the establis hed invalidation of time data in contrast to the supply voltage monitoring circuit intended to confirm the potential invalidation of time data. further, the supply voltage monitoring circuit can be applied to battery supply voltage monitoring.
r2045s/d 9 ? periodic interrupt function the r2045s/d incorporates the periodic interrupt circ uit configured to generate periodic interrupt signals aside from interrupt signals generated by the periodic interrupt circuit for output from the intr pin. periodic interrupt signals have five selectable frequency settings of 2 hz (once per 0.5 seconds), 1 hz (once per 1 second), 1/60 hz (once per 1 minute), 1/3600 hz (once per 1 hour), and monthly (the first day of every month). further, periodic interrupt signals also have two select able waveforms, a normal pulse form (with a frequency of 2 hz or 1 hz) and special form adapted to interruption from the cpu in the level mode (with second, minute, hour, and month interrupts). the condition of periodic interrupt signals can be monitored by using a polling function. ? 32khz clock output the r2045s/d incorporates a 32-khz clock circuit configured to generate clock pulses with the oscillation frequency of a 32.768khz crystal oscillator for output from the 32kout pin. the 32-khz clock output can be disabled by certain register settings but cannot be di sabled without manipulation of any two registers with different addresses to prevent disabling in such events as the runaway of the cpu.
r2045s/d 10 address mapping address register name d a t a a3a2a1a0 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 second counter - *2) s40 s20 s10 s8 s4 s2 s1 1 0 0 0 1 minute counter - m40 m20 m10 m8 m4 m2 m1 2 0 0 1 0 hour counter - - h20 p/ a h10 h8 h4 h2 h1 3 0 0 1 1 day-of-week counter - - - - - w4 w2 w1 4 0 1 0 0 day-of-month counter - - d20 d10 d8 d4 d2 d1 5 0 1 0 1 month counter and century bit 19 /20 - - mo10 mo8 mo4 mo2 mo1 6 0 1 1 0 year counter y80 y40 y20 y10 y8 y4 y2 y1 7 0 1 1 1 oscillation adjustment register *3) (0) *4) f6 f5 f4 f3 f2 f1 f0 8 1 0 0 0 alarm_w (minute register) - wm40 wm20 wm10 wm8 wm4 wm2 wm1 9 1 0 0 1 alarm_w (hour register) - - wh20 wp/ a wh10 wh8 wh4 wh2 wh1 a 1 0 1 0 alarm_w (day-of-week register) - ww6 ww5 ww4 ww3 ww2 ww1 ww0 b 1 0 1 1 alarm_d (minute register) - dm40 dm20 dm10 dm8 dm4 dm2 dm1 c 1 1 0 0 alarm_d (hour register) - - dh20 dp/ a dh10 dh8 dh4 dh2 dh1 d 1 1 0 1 - - - - - - - - e 1 1 1 0 control register 1 *3) wale dale 12 /24 clen2 test ct2 ct1 ct0 f 1 1 1 1 control register 2 *3) vdsl vdet xst pon *5) clen1 ctfg wafg dafg notes: *1) all the data listed above ac cept both reading and writing. *2) the data marked with "-" is invalid for writing and reset to 0 for reading. *3) when the pon bit is set to 1 in control register 2, all the bits are reset to 0 in oscillation adjustment register, control register 1 and control register 2 excluding the xst and pon bits. *4) the (0) bit should be set to 0. *5) xst is oscillation halt sensing bit. *6) pon is power-on reset flag.
r2045s/d 11 register settings ? control register 1 (address eh) d7 d6 d5 d4 d3 d2 d1 d0 wale dale 12 /24 clen2 test ct2 ct1 ct0 (for writing) wale dale 12 /24 clen2 test ct2 ct1 ct0 (for reading) 0 0 0 0 0 0 0 0 default settings *) *) default settings: default value means read / written values when the pon bit is set to ?1? due to vdd power-on from 0 volts. (1) wale, dale alarm_w enable bit, alarm_d enable bit wale,dale description 0 disabling the alarm interrupt circui t (under the control of the settings of the alarm_w registers and the alarm_d registers). (default) 1 enabling the alarm interrupt circui t (under the control of the settings of the alarm_w registers a nd the alarm_d registers) (2) 12 /24 12 /24-hour mode selection bit 12 /24 description 0 selecting the 12-hour mode with a.m. and p.m. indications. (default) 1 selecting the 24-hour mode setting the 12 /24 bit to 0 and 1 specifies the 12-hour mode and the 24-hour mode, respectively. 24-hour mode 12-hour mode 24-hour mode 12-hour mode 00 12 (am12) 12 32 (pm12) 01 01 (am 1) 13 21 (pm 1) 02 02 (am 2) 14 22 (pm 2) 03 03 (am 3) 15 23 (pm 3) 04 04 (am 4) 16 24 (pm 4) 05 05 (am 5) 17 25 (pm 5) 06 06 (am 6) 18 26 (pm 6) 07 07 (am 7) 19 27 (pm 7) 08 08 (am 8) 20 28 (pm 8) 09 09 (am 9) 21 29 (pm 9) 10 10 (am10) 22 30 (pm10) 11 11 (am11) 23 31 (pm11) setting the 12 /24 bit should precede writing time data (3) clen2 32-khz clock output bit2 clen2 description 0 enabling the 32-khz cl ock output (default) 1 disabling the 32- khz clock output setting the clen2 bits or the clen1 bit (d3 in the control register 2) to 0 specifies generating clock pulses with the oscillation frequency of the 32.768-khz crystal oscillato r for output from the 32kout pin. conversely, setting both the clen1 and the clen2 bit to 1 specifies disabling (?h?) such output.
r2045s/d 12 (4) test test bit test description 0 normal operation mode. (default) 1 test mode. the test bit is used only for testing in the factory and should normally be set to 0. (5) ct2,ct1, and ct0 periodic interrupt selection bits description ct2 ct1 ct0 wave form mode interrupt cycle and falling timing 0 0 0 - off(h) (default) 0 0 1 - fixed at ?l? 0 1 0 pulse mode *1) 2hz(duty50%) 0 1 1 pulse mode *1) 1hz(duty50%) 1 0 0 level mode *2) once per 1 second (synchronized with second counter increment) 1 0 1 level mode *2) once per 1 minute (at 00 seconds of every minute) 1 1 0 level mode *2) once per hour (at 00 minutes and 00 seconds of every hour) 1 1 1 level mode *2) once per month (at 00 hours, 00 minutes, and 00 seconds of first day of every month) * 1) pulse mode: 2-hz and 1-hz clock pulses are out put in synchronization with the increment of the second counter as illustrated in the timing chart below. intr pin rewriting of the second counter ctfg bit a pprox. 92 s (increment of second counter) in the pulse mode, the increment of the second counter is delayed by approximately 92 s from the falling edge of clock pulses. consequently, time readings immediately after the falling edge of clock pulses may appear to lag behind the time counts of the real-time clocks by approximately 1 second. rewriting the second counter will reset the other time counters of less than 1 second, driving the intr pin low. * 2) level mode: periodic interrupt signals are output with selectable interrupt cycle settings of 1 second, 1 minute, 1 hour, and 1 month. the increment of the second counter is synchronized with the falling edge of periodic interrupt signals. for example, periodic interrupt signals with an interrupt cycle setting of 1 second are output in synchronization with the increment of the second counter as illustrated in the timing chart below.
r2045s/d 13 ctfg bit intr pin setting ctfg bit to 0 setting ctfg bit to 0 (increment of second counter) (increment of second counter) (increment of second counter) *1), *2) when the oscillation adjustment circuit is us ed, the interrupt cycle will fluctuate once per 60sec. as follows: pulse mode: the ?l? period of output pul ses will increment or decr ement by a maximum of 3.784 ms. for example, 1-hz clock pulses will have a duty cycle of 50 0.3784%. level mode: a periodic interrupt cycle of 1 second will increment or decrement by a maximum of 3.784 ms. ? control register 2 (address fh) d7 d6 d5 d4 d3 d2 d1 d0 vdsl vdet xst pon clen1 ctfg waf g dafg (for writing) vdsl vdet xst pon clen1 ctfg waf g dafg (for reading) 0 0 indefinite 1 0 0 0 0 default settings *) *) default settings: default value means read / wri tten values when the pon bit is set to ?1? due to vdd power-on from 0 volts. (1) vdsl vdd supply voltage monitoring threshold selection bit vdsl description 0 selecting the vdd supply voltage monitori ng threshold setting of 2.1v. (default) 1 selecting the vdd supply voltage moni toring threshold setting of 1.3v. the vdsl bit is intended to select the vdd supply voltage monitoring threshold settings. (2) vdet supply voltage monitoring result indication bit vdet description 0 indicating supply voltage above the supply voltage monitoring threshold settings. (default) 1 indicating supply voltage below the supply voltage monitoring threshold settings. once the vdet bit is set to 1, the supply voltage m onitoring circuit will be disabled while the vdet bit will hold the setting of 1. the vdet bit accepts only t he writing of 0, which restarts the supply voltage monitoring circuit. conversely, setting the vdet bit to 1 causes no event. (3) xst oscillation halt sensing monitor bit xst description 0 sensing a halt of oscillation 1 sensing a normal condition of oscillation
r2045s/d 14 the xst accepts the reading and writing of 0 and 1. the xst bit will be set to 0 when the oscillation halt sensing. the xst bit will hold 0 even after t he restart of oscillation. (4) pon power-on-reset flag bit pon description 0 normal condition 1 detecting vdd power-on -reset (default) the pon bit is for sensing power-on reset condition. * the pon bit will be set to 1 when vdd power-on from 0 volts. the pon bit will hold the setting of 1 even after power-on. * when the pon bit is set to 1, all bits will be reset to 0, in the os cillation adjustment register, control register 1, and control register 2, except xst and pon. as a result, intr pin stops outputting, and 32kout starts outputting. * the pon bit accepts only the writing of 0. conv ersely, setting the pon bit to 1 causes no event. (5) clen1 32-khz clock output bit 1 clen1 description 0 enabling the 32-kh z clock output (default) 1 disabling the 32- khz clock output setting the clen1 bit or the clen2 bit (d4 in the control register 1) to 0 specifies generating clock pulses with the oscillation frequency of the 32.768-khz crystal oscillator for output from the 32kout pin. conversely, setting both the clen1 and the clen2 bit to 1 specifies disabling (?h?) such output. (6) ctfg periodic interrupt flag bit ctfg description 0 periodic interrupt output = ?h? (default) 1 periodic interrupt output = ?l? the ctfg bit is set to 1 when the periodic interrupt signals are output from the intr pin (?l?). the ctfg bit accepts only the writing of 0 in the level mode, which disables (?h?) the intr pin until it is enabled (?l?) again in the next interrupt cycle. conver sely, setting the ctfg bit to 1 causes no event. (7) wafg,dafg alarm_w flag bit and alarm_d flag bit wafg,dafg description 0 indicating a mismatch between current time and preset alarm time (default) 1 indicating a match between current time and preset alarm time the wafg and dafg bits are valid only when the wale and dale have the setting of 1, which is caused approximately 61 s after any match between current time and pr eset alarm time specified by the alarm_w registers and the alarm_d regist ers. the wafg (dafg) bit ac cepts only the writing of 0. intr pin outputs off (?h?) when this bit is set to 0. and intr pin outputs ?l? again at the next preset alarm time. conversely, setting the wafg and dafg bits to 1 ca uses no event. the wafg and dafg bits will have the reading of 0 when the alarm interrupt circuit is disabled with the wale and dale bits set to 0. the settings of the wafg (dafg) bit is synchronized with the output of the intr pin as shown in the timing chart below.
r2045s/d 15 intr pin writing of 0 to wafg(dafg) bit wafg(dafg) bit (match between current time and preset alarm time) a pprox. 61 s a pprox. 61 s writing of 0 to wafg(dafg) bit (match between current time and preset alarm time) (match between current time and preset alarm time) ? time counter (address 0-2h) second counter (address 0h) d7 d6 d5 d4 d3 d2 d1 d0 - s40 s20 s10 s8 s4 s2 s1 (for writing) 0 s40 s20 s10 s8 s4 s2 s1 (for reading) 0 indefi nite indefi nite indefi nite indefi nite indefi nite indefi nite indefi nite default settings *) minute counter (address 1h) d7 d6 d5 d4 d3 d2 d1 d0 - m40 m20 m10 m8 m4 m2 m1 (for writing) 0 m40 m20 m10 m8 m4 m2 m1 (for reading) 0 indefi nite indefi nite indefi nite indefi nite indefi nite indefi nite indefi nite default settings *) hour counter (address 2h) d7 d6 d5 d4 d3 d2 d1 d0 - - p/ a or h20 h10 h8 h4 h2 h1 (for writing) 0 0 p/ a or h20 h10 h8 h4 h2 h1 (for reading) 0 0 indefi nite indefi nite indefi nite indefi nite indefi nite indefi nite default settings *) *) default settings: default value means read / writt en values when the pon bit is set to ?1? due to vdd power-on from 0 volts. * time digit display (bcd format) as follows: the second digits range from 00 to 59 and are carri ed to the minute digit in transition from 59 to 00. the minute digits range from 00 to 59 and are carri ed to the hour digits in transition from 59 to 00. the hour digits range as shown in "p11 ? control register 1 (address eh) (2) 12 /24: 12 -24-hour mode selection bit" and are carried to the day-of-mont h and day-of-week digits in transition from pm11 to am12 or from 23 to 00.
r2045s/d 16 * any writing to the second counter resets divider units of less than 1 second. * any carry from lower digits with the writing of non-existent time may cause the time counters to malfunction. therefore, such incorrect writing should be replaced with the writing of existent time data. ? day-of-week counter (address 3h) d7 d6 d5 d4 d3 d2 d1 d0 - - - - - w4 w2 w1 (for writing) 0 0 0 0 0 w4 w2 w1 (for reading) 0 0 0 0 0 indefi nite indefi nite indefi nite default settings *) *) default settings: default value means read / writt en values when the pon bit is set to ?1? due to vdd power-on from 0 volts. * the day-of-week counter is increm ented by 1 when the day-of-week digi ts are carried to the day-of-month digits. * day-of-week display (incremented in septimal notation): (w4, w2, w1) = (0, 0, 0) (0, 0, 1) ? (1, 1, 0) (0, 0, 0) * correspondences between days of the week an d the day-of-week digits are user-definable (e.g. sunday = 0, 0, 0) * the writing of (1, 1, 1) to (w4, w2, w1) is pr ohibited except when days of the week are unused. ? calendar counter (address 4-6h) day-of-month counter (address 4h) d7 d6 d5 d4 d3 d2 d1 d0 - - d20 d10 d8 d4 d2 d1 (for writing) 0 0 d20 d10 d8 d4 d2 d1 (for reading) 0 0 indefi nite indefi nite indefi nite indefi nite indefi nite indefi nite default settings *) month counter + century bit (address 5h) d7 d6 d5 d4 d3 d2 d1 d0 19 /20 - - mo10 mo8 mo4 mo2 mo1 (for writing) 19 /20 0 0 mo10 mo8 mo4 mo2 mo1 (for reading) indefi nite 0 0 indefi nite indefi nite indefi nite indefi nite indefi nite default settings *) year counter (address 6h) d7 d6 d5 d4 d3 d2 d1 d0 y80 y40 y20 y10 y8 y4 y2 y1 (for writing) y80 y40 y20 y10 y8 y4 y2 y1 (for reading) indefi nite indefi nite indefi nite indefi nite indefi nite indefi nite indefi nite indefi nite default settings *) *) default settings: default value means read / writt en values when the pon bit is set to ?1? due to vdd power-on from 0 volts. * the calendar counters are configured to display the calendar digits in bcd form at by using the automatic
r2045s/d 17 calendar function as follows: the day-of-month digits (d20 to d1) range from 1 to 31 for january, march, may, july, august, october, and december; from 1 to 30 for april, june, september, and november; from 1 to 29 for february in leap years; from 1 to 28 for february in ordinary years. the day-of-month di gits are carried to the month digits in reversion from the last day of t he month to 1. the month digits (mo10 to mo1) range from 1 to 12 and are carried to the year digits in reversion from 12 to 1. the year digits (y80 to y1) range from 00 to 99 (00, 04, 08, , 92, and 96 in leap years) and are carried to the 19 /20 digits in reversion from 99 to 00. the 19 /20 digits cycle between 0 and 1 in reversion from 99 to 00 in the year digits. * any carry from lower digits with the writing of non-e xistent calendar data may cause the calendar counters to malfunction. therefore, such incorrect writing sh ould be replaced with the writ ing of existent calendar data. ? oscillation adjustment register (address 7h) d7 d6 d5 d4 d3 d2 d1 d0 (0) f6 f5 f4 f3 f2 f1 f0 (for writing) 0 f6 f5 f4 f3 f2 f1 f0 (for reading) 0 0 0 0 0 0 0 0 default settings *) *) default settings: default value means read / writt en values when the pon bit is set to ?1? due to vdd power-on from 0 volts. (0) bit: (0) bit should be set to 0 f6 to f0 bits: * the oscillation adjustment circuit is configured to change time counts of 1 second on the basis of the settings of the oscillation adjustme nt register when the se cond digits read 00, 20, or 40 seconds. normally, the second counter is incremented once per 32768 32.768-khz clock pul ses generated by the crystal oscillator. writing to the f6 to f0 bi ts activates the oscillation adjustment circuit. * the oscillation adjustment circuit will not operate with the same timing (00, 20, or 40 seconds) as the timing of writing to the oscillation adjustment register. * the f6 bit setting of 0 causes an increment of time counts by ((f5, f4, f3, f2, f1, f0) - 1) x 2. the f6 bit setting of 1 causes a decrement of time counts by (( f 5 , f 4 , f 3 , f 2 , f 1 , f 0 ) + 1) x 2. the settings of "*, 0, 0, 0, 0, 0, *" ("*" representing ei ther "0" or "1") in the f6, f5, f4, f3, f2, f1, and f0 bits cause neither an increment nor decrement of time counts. example: when the second digits read 00, 20, or 40, the settings of "0, 0, 0, 0, 1, 1, 1" in the f6, f5, f4, f3, f2, f1, and f0 bits cause an increment of t he current time counts of 32768 by (7 - 1) x 2 to 32780 (a current time count loss). when the second digits read 00, 20, or 40, the settings of "0, 0, 0, 0, 0, 0, 1" in the f6, f5, f4, f3, f2, f1, and f0 bits cause neither an increment nor a decrement of the current time counts of 32768. when the second digits read 00, 20, or 40, the settings of "1, 1, 1, 1, 1, 1, 0" in the f6, f5, f4, f3, f2, f1, and f0 bits cause a decrement of the current time c ounts of 32768 by (- 2) x 2 to 32764 (a current time count gain). an increase of two clock pulses once per 20 seconds causes a time count loss of approximately 3 ppm (2 /
r2045s/d 18 (32768 x 20 = 3.051 ppm). conversely, a decrease of two clock pulses once per 20 seconds causes a time count gain of 3 ppm. consequently, deviations in time counts can be corrected with a precision of 1.5 ppm. note that the oscillation adjustment circuit is configured to correct deviations in time counts and not the oscillation frequency of the 32.768-khz clock pulses. fo r further details, see "p28 configuration of oscillation circuit a nd correction of time count deviations ? oscillation adjustment circuit". ? alarm_w registers (address 8-ah) alarm_w minute register (address 8h) d7 d6 d5 d4 d3 d2 d1 d0 - wm40 wm20 wm10 wm8 wm4 wm2 wm1 (for writing) 0 wm40 wm20 wm10 wm8 wm4 wm2 wm1 (for reading) 0 indefi nite indefi nite indefin ite indefi nite indefi nite indefi nite indefi nite default settings *) alarm_w hour register (address 9h) d7 d6 d5 d4 d3 d2 d1 d0 - - wh20 wp/ a wh10 wh8 wh4 wh2 wh1 (for writing) 0 0 wh20 wp/ a wh10 wh8 wh4 wh2 wh1 (for reading) 0 0 indefi nite indefi nite indefi nite indefi nite indefi nite indefi nite default settings *) alarm_w day-of-week register (address ah) d7 d6 d5 d4 d3 d2 d1 d0 - ww6 ww5 ww4 ww3 ww2 ww1 ww0 (for writing) 0 ww6 ww5 ww4 ww3 ww2 ww 1 ww0 (for reading) 0 indefi nite indefi nite indefi nite indefi nite indefi nite indefi nite indefi nite default settings *) *) default settings: default value means read / writt en values when the pon bit is set to ?1? due to vdd power-on from 0 volts. * the d5 bit of the alarm_w hour register represents wp/ a when the 12-hour mode is selected (0 for a.m. and 1 for p.m.) and wh20 when the 24-hour mode is selected (tens in the hour digits). * the alarm_w registers should not have any non-existent alarm time settings. (note that any mismatch between current time and pres et alarm time specified by the alarm_w registers may disable the alarm interrupt circuit.) * when the 12-hour mode is selected, the hour digits read 12 and 32 for 0 a.m. and 0 p.m., respectively. (see "p11 ? control register 1 (address eh) (2) 12 /24: 12-/24-hour mode selection bit") * ww0 to ww6 correspond to w4, w2, and w1 of the day-o f-week counter with settings ranging from (0, 0, 0) to (1, 1, 0). * ww0 to ww6 with respective settings of 0 disable the outputs of the alarm_w registers.
r2045s/d 19 example of alarm time setting alarm day-of-week 12-hour mode 24-hour mode preset alarm time sun. mon. tue. wed. th. fri. sat. 10 hr. 1 hr. 10 min . 1 min . 10 hr. 1 hr. 10 min . 1 min. ww 0 ww 1 ww 2 ww 3 ww 4 ww 5 ww 6 00:00 a.m. on all days 1 1 1 1 1 1 1 1 2 0 0 0 0 0 0 01:30 a.m. on all days 1 1 1 1 1 1 1 0 1 3 0 0 1 3 0 11:59 a.m. on all days 1 1 1 1 1 1 1 1 1 5 9 1 1 5 9 00:00 p.m. on mon. to fri. 0 1 1 1 1 1 0 3 2 0 0 1 2 0 0 01:30 p.m. on sun. 1 0 0 0 0 0 0 2 1 3 0 1 3 3 0 11:59 p.m. on mon. ,wed., and fri. 0 1 0 1 0 1 0 3 1 5 9 2 3 5 9 note that the correspondence betw een ww0 to ww6 and the days of the we ek shown in the above table is only an example and not mandatory. ? alarm_d register (address b-ch) alarm_d minute register (address bh) d7 d6 d5 d4 d3 d2 d1 d0 - dm40 dm20 dm10 dm8 dm4 dm2 dm1 (for writing) 0 dm40 dm20 dm10 dm8 dm4 dm2 dm1 (for reading) 0 indefinit e indefinit e indefinit e indefinit e indefinit e indefinit e indefinit e default settings *) alarm_d hour register (address ch) d7 d6 d5 d4 d3 d2 d1 d0 - - dh20 dp/ a dh10 dh8 dh4 dh2 dh 1 (for writing) 0 0 dh20 dp/ a dh10 dh8 dh4 dh2 dh1 (for reading) 0 0 indefini te indefinit e indefinit e indefinit e indefinit e indefinit e default settings *) *) default settings: default value means read / writt en values when the pon bit is set to ?1? due to vdd power-on from 0 volts.
r2045s/d 20 * the d5 bit represents dp/ a when the 12-hour mode is selected (0 for a.m. and 1 for p.m.) and dh20 when the 24-hour mode is selected (tens in the hour digits). * the alarm_d registers should not have any non-existent alarm time settings. (note that any mismatch between current time and pr eset alarm time specified by the alarm_d registers may disable the alarm interrupt circuit.) * when the 12-hour mode is selected, the hour digits read 12 and 32 for 0a.m. and 0p.m., respectively. (see "p11 ? control register 1 (address eh) (2) 12 /24: 12/24-hour mode selection bit")
r2045s/d 21 interfacing with the cpu ? data transfer formats (1) timing between ce pin transition and data input / output the r2045s/d adopts a 4-wire serial interface by which they use the ce (chip enable), sclk (serial clock), si (serial input), and so (serial output) pins to rece ive and send data to and from the cpu. the 4-wire serial interface provides two types of input/output timings with which the so pin output and the si pin input are synchronized with the rising or fallin g edges of the sclk pin input, respecti vely, and vice versa. the r2045s/d is configured to select either one of two different input/output timings dependi ng on the level of the sclk pin in the low to high transition of the ce pin. namely, when t he sclk pin is held low in the low to high transition of the ce pin, the models will select the timing with which t he so pin output is synchronized with the rising edge of the sclk pin input, and the si pin input is synchronized wi th the falling edge of the sclk pin input, as illustrated in the timing chart below. sclk so t ds si ce t ces t dh t rd conversely, when the sclk pin is held high in the low to high transition of the ce pin, the models will select the timing with which the so pin output is synchronized with the falling edge of the sclk pin input, and the si pin input is synchronized with the rising edge of the sc lk pin input, as illustrated in the timing chart below. sclk so t ds si ce t ces t dh t rd (2) data transfer formats data transfer is commenced in the low to high transiti on of the ce pin input and completed in its high to low transition. data transfer is conducted serially in multiple units of 1 byte (8 bits). the former 4 bits are used to specify in the address pointer a head address with which data transfer is to be commenced from the host. the latter 4 bits are used to select either reading data transfe r or writing data transfer, and to set the transfer format register to specify an appropriate data transfer format. all data transfer formats are designed to transfer the most significant bit (msb) first.
r2045s/d 22 a2 ce scl k so 6 a1 a0 c3 c2 c1 c0 d7 d6 d3 d2 d1 d0 a3 7 5 8 2 3 1 2 3 1 4 d7 d6 d3 d2 d1 d0 reading data transfer setting the address pointe r writing data transfer setting the transfer format register si two types of data transfer formats are available for reading data transfer and writing data transfer each. ? writing data transfer formats (1) 1-byte writing data transfer format the first type of writing data transfer format is design ed to transfer 1-byte data at a time and can be selected by specifying in the address pointer a head address with which writing data transfer is to be commenced and then writing the setting of 8h to the transfer format regist er. this 1-byte writing data transfer can be completed by driving the ce pin low or continued by specifying a new head address in the address pointer and setting the data transfer format. 1 1 data data example of 1-byte writing data transfer (for writing data to addresses fh and 7h) data transfer from the host ce data transfer from the rtcs so specifying 7h in the a ddress pointer 0 1 0 0 1 1 setting 8h in the transfer format register writing data to address fh writing data to address 7h 0 1 1 0 0 0 1 1 specifying fh in the a ddress pointer setting 8h in the transfer format register si
r2045s/d 23 (2) burst writing data transfer format the second type of writing data transfer format is desi gned to transfer a sequence of data serially and can be selected by specifying in the address pointer a head add ress with which writing data transfer is to be commenced and then writing the setting of 0h to the tran sfer format register. the address pointer is incremented for each transfer of 1-byte data and cycled from fh to 0h. this burst writing data transfer can be completed by driving the ce pin low. 1 0 data data example of burst writing data transfer (for writing data to addresses eh, fh, and 0h) ce so 0 0 0 0 1 1 si data data transfer from the host data transfer from the rtcs writing data to address eh specifying eh in the a ddress pointer setting 0h in the transfer format register writing data to address fh writing data to address 0h ? reading data transfer formats (1) 1-byte reading data transfer format the first type of reading data transfer format is design ed to transfer 1-byte data at a time and can be selected by specifying in the address pointer a head address with which reading data transfer is to be commenced and then the setting of writing ch to the transfer format register. this 1-byte reading data transfer can be completed by driving the ce pin low or continued by specifying a new he ad address in the address pointer and selecting this type of reading data transfer format. 1 0 data data example of 1-byte reading data transfer (for reading data from addresses eh and 2h) ce so 1 1 0 0 1 1 0 1 0 1 0 0 0 1 si data transfer from the host data transfer from the rtcs specifying 2h in the a ddress pointer setting ch in the transfer format register reading data from address eh reading data from address 2h specifying eh in the a ddress pointer setting ch in the transfer format register
r2045s/d 24 (2) burst reading data transfer format the second type of reading data transfer format is desi gned to transfer a sequence of data serially and can be selected by specifying in the address pointer a head address with which reading data transfer is to be commenced and then writing the setting of 4h to the tran sfer format register. the address pointer is incremented for each transfer of 1-byte data and cycled from fh to 0h. this burst reading data transfer can be completed by driving the ce pin low. 1 1 data data example of burst reading data transfer (for reading data from addresses fh, 0h, and 1h) ce so 1 0 0 0 1 1 data si data transfer from the host data transfer from the rtcs reading data from address fh specifying fh in the a ddress pointer setting 4h in the transfer format register reading data from address 0h reading data from address 1h (3) combination of 1-byte reading and writing data transfer formats the 1-byte reading and writing data transfer formats can be combined together and further followed by any other data transfer format. 1 1 data example of reading modify writing data transfer (for reading and writing data from and to address fh) ce so 1 1 0 0 1 1 1 1 1 0 0 0 1 1 data si data transfer from the host data transfer from the rtcs writing data to address fh specifying fh in the a ddress pointer setting 8h in the transfer format register specifying fh in the a ddress pointer setting ch in the transfer format register reading data from address fh
r2045s/d 25 the reading and writing data transfer formats correspond to the settings in the transfer format register as shown in the table below. 1 byte burst writing data transfer 8h (1,0,0,0) 0h (0,0,0,0) reading data transfer ch (1,1,0,0) 4h (0,1,0,0)
r2045s/d 26 ? considerations in reading and writing time data under special condition any carry to the second digits in the process of read ing or writing time data may cause reading or writing erroneous time data. for example, suppose a carry ou t of 13:59:59 into 14:00:00 o ccurs in the process of reading time data in the middle of shifting from the minute digits to the hour digits. at this moment, the second digits, the minute digits, and the hour digits read 59 seco nds, 59 minutes, and 14 hours, respectively (indicating 14:59:59) to cause the reading of time data deviating from actual time virtually 1 hour. a similar error also occurs in writing time data. to prevent such errors in reading and writing time data, the r2045s/d has the function of temporarily locking any carry to the second di gits during the high interval of the ce pin and unlocking such a carry in its high to low transiti on. note that a carry to the second digits can be locked for only 1 second, during which time the ce pin should be driven low. ce time counts within rtc 14:00:01 actual time 13:59:59 max.62 s 14:00:00 13:59:59 14:00:00 14:00:01 the effective use of this function requires the followi ng considerations in reading and writing time data: (1) hold the ce pin high in each session of reading or writing time data. (2) ensure that the high interval of the ce pin lasts within 1 second. should t here be any possibility of the host going down in the process of reading or writing time data, make arrangements in the peripheral circuitry as to drive the ce pin low or open at the mo ment that the host actually goes down. (3) leave a time span of 31 s or more from the low to high transition of the ce pin to the start of access to addresses 0h to 6h in order that any ongoing carry of the time digits may be completed within this time span. (4) leave a time span of 62 s or more from the high to low transition of the ce pin to its low to high transition in order that any ongoing carry of the time digits during t he high interval of the ce pin may be adjusted within this time span. the considerations listed in (1), (3), and (4) above are not required when the process of reading or writing time data is obviously free from any carry of the time digits. (e.g. reading or writing time data in synchronization with the periodic interrupt function in the level mode or the alarm interrupt function). good and bad examples of reading and writing ti me data are illustrated on the next page.
r2045s/d 27 so 0ch data data bad example (1) (where the ce pin is once driven low in the process of reading time data) less than 62 s so f0h ce time span of less than 31 s writing to a ddress 0h (sec.) 0ch ce bad example (3) (where a time span of less than 61 s is left between the adjacent processes of reading time data) good example so data f4h data data ce a ddress pointe r = 1h transfer format register = 4h time span of 31 s or more reading from a ddress 1h (min.) data so 0ch data data 31 s or more reading from a ddress 1h (min.) data 14h 31 s or more ce data transfer from rtcs 0ch data data transfer from the host bad example (2) (where a time span of less than 31 s is left until the start of the process of writing time data) a ny address other than addresses 0h to 6h permits of immediate reading or writing without requiring a time span of 31 s. si si si si data data data data reading from a ddress fh (control2) reading from a ddress 0h (sec.) reading from a ddress 2h (hr.) a ddress pointe r = fh transfer format register = 4h a ddress pointe r = fh transfer format register = 0h reading from a ddress 0h (sec.) reading from a ddress 2h (hr.) a ddress pointe r = 0h transfer format register = ch writing to a ddress 1h (min.) writing to a ddress 2h (hr.) writing to a ddress fh (contorl2) a ddress pointe r = 0h transfer format register = ch reading from a ddress 0h (sec.) reading from a ddress 0h (sec.) a ddress pointe r = 0h transfer format register = ch
r2045s/d 28 correction of time count deviations ? the necessity for correction of time count deviations the oscillation frequency for r2045s/d is corrected to 0 5ppm at 25 c in fabrication. oscillation frequency is the fastest at 25 c, (please see typical characteristics oscillation frequency de viation vs. operating temperature (p.42)). in normal condition, temper ature is not kept constant at 25 c. that is, r2045s/d loses without correction of time counts deviation. gene rally, a clock is corrected to gain 3 to 6ppm at 25 c. r2045s/d is corrected it by setting clock adjustment regi ster. ricoh suggests to set 7fh to clock adjustment register (address 7h) for time setting to gain 3ppm at 25 c, for the equipment used indoors. and suggests to set 7eh to clock adjustment register (add ress 7h) for time setting to gain 6ppm at 25 c, for the equipment used outdoors. ? measurement of oscillation frequency frequency counter 32kout vss vdd * 1) when power-on, the r2045s/d is configured to generate 32.768-khz clock pulses for output from the 32kout pin. * 2) a frequency counter with 6 (more preferably 7) or more digits on the order of 1ppm is recommended for use in the measurement of the oscillation frequency of the oscillation circuit. ? oscillation adjustment circuit the oscillation adjustment circuit can be used to correct a time count gain or loss with high precision by varying the number of 1-se cond clock pulses once per 20 seconds. the oscillation adjustment circuit can be disabled by writing the settings of "*, 0, 0, 0, 0, 0, *" (" *" representing "0" or "1") to the f6, f5, f4, f3, f2, f1, and f0 bits in the oscillation adjustment circuit. converse ly, when such oscillation adjustment is to be made, an appropriate oscillation adjustment valu e can be calculated by the equation below for writing to the oscillation adjustment circuit. (1) when oscillation frequency (* 1) is higher than target frequency (* 2) (causing time count gain) oscillation adjustment value (*3) = (oscillation frequency - target frequency + 0.1) oscillation frequency 3.051 10 -6 (oscillation frequency ? target frequency) 10 + 1
r2045s/d 29 * 1) oscillation frequency: frequency of clock pulse output fr om the 32kout pin at normal temper ature in the manner described in " p28 ? measurement of oscillation frequency". * 2) target frequency: desired frequency to be set. generally, a 32.768- khz crystal oscillator has such temperature characteristics as to have the highest oscillation fr equency at normal temperature. consequently, the crystal oscillator is recommended to have target frequency settings on the order of 32.768 to 32.76810 khz (+3.05ppm relative to 32.768 khz). note that the target frequency differs depending on the environment or location where the equipment incorporati ng the rtc is expected to be operated. * 3) oscillation adjustment value: value that is to be finally written to the f0 to f6 bits in the oscillation ad justment regi ster and is represented in 7-bit coded decimal notation. (2) when oscillation frequency is equal to target fr equency (causing time count neither gain nor loss) oscillation adjustment value = 0, +1, -64, or ?63 (3) when oscillation frequency is lower than target frequency (causing time count loss) oscillation adjustment value = (oscilla tion frequency - target frequency) oscillation frequency 3.051 10 -6 (oscillation frequency ? target frequency) 10 oscillation adjustment value calcul ations are exemplified below (a) for an oscillation frequency = 32768.85hz and a target frequency = 32768.05hz oscillation adjustment value = (32768.85 - 32768.05 + 0.1) / (32768.85 3.051 10 -6 ) (32768.85 - 32768.05) 10 + 1 = 9.001 9 in this instance, write the settings ((0),f6,f5,f4,f3,f2,f1,f0)=(0,0,0,0,1 ,0,0,1) in the oscillation adjustment register. thus, an appropriate oscillation adjustment val ue in the presence of any time count gain represents a distance from 01h. (b) for an oscillation frequency = 32762.22hz and a target frequency = 32768.05hz oscillation adjustment value = (32762.22 - 32768.05) / (32762.22 3.051 10 -6 ) (32762.22 - 32768.05) 10 = -58.325 -58 to represent an oscillation adjustment value of - 58 in 7-bit coded decimal notation, subtract 58 (3ah) from 128 (80h) to obtain 46h. in this instance, write the settings of ((0),f6,f5,f4,f3,f2,f1,f0) = (0,1,0,0,0,1,1,0) in the oscillation adjustment register. thus, an appropriate os cillation adjustment value in the presence of any time count loss represents a distance from 80h. notes: 1) oscillation adjustment does not affect the fr equency of 32.768-khz clock pulses output from the 32kout pin. 2) oscillation adjustment value range: when the osc illation frequency is higher than the target frequency (causing a time count gain), an appropriate time coun t gain ranges from -3.05ppm to -189.2ppm with the settings of "0, 0, 0, 0, 0, 1, 0" to "0, 1, 1, 1, 1, 1, 1" written to the f6, f5, f4, f3, f2, f1, and f0 bits in the oscillation adjustment register, thus allowing corr ection of a time count gain of up to +189.2ppm.
r2045s/d 30 conversely, when the oscillation frequency is lower t han the target frequency (causing a time count loss), an appropriate time count gain ranges from +3.05ppm to + 189.2ppm with the settings of "1, 1, 1, 1, 1, 1, 1" to "1, 0, 0, 0, 0, 1, 0" written to the f6, f5, f4, f3 , f2, f1, and f0 bits in the oscillation adjustment register, thus allowing correction of a time count loss of up to -189.2ppm. 3) if following 3 conditions are completed, actual cl ock adjustment value could be different from target adjustment value that set by oscillator adjustment function. 1. using oscillator adjustment function 2. access to r2045s/d at random, or synchronized with external clock that has no relation to r2045s/d, or synchronized with periodic interrupt in pulse mode. 3. access to r2045s/d more than 2 times per each second on average. for more details, please contact to ricoh. ? how to evaluate the clock gain or loss the oscillator adjustment circuit is configured to change time counts of 1 second on the basis of the settings of the oscillation adjustment register once in 20 seconds. the oscillation adj ustment circuit does not effect the frequency of 32768hz-clock pulse output from the 32out pin. therefore, afte r writing the oscillation adjustment register, we cannot meas ure the clock error with probing 32kou t clock pulses. the way to measure the clock error as follows: (1) output a 1hz clock pulse of pulse mode with interrupt pin set (0,0,x,x,0,0,1,1) to control register 1 at address eh. (2) after setting the oscillation adjustment register, 1h z clock period chan ges every 20seconds ( or every 60 seconds) like next page figure. 1hz clock pulse t0 t0 t0 t1 1 time 19 times measure the interval of t0 and t1 with frequency counte r. a frequency counter with 7 or more digits is recommended for the measurement. (3) calculate the typical period from t0 and t1 t = (19 t0+1 t1)/20 calculate the time error from t.
r2045s/d 31 power-on reset, oscillation halt sensing, and supply voltage monitoring ? pon, xst , and vdet the power-on reset circuit is configured to reset c ontrol register1, 2, and clo ck adjustment register when v dd power up from 0v. the oscillation halt sensing circuit is configured to record a halt on oscillation by 32.768-khz clock pulses. the supply voltage monitoring circuit is configured to record a drop in supply voltage below a threshold voltage of 2.1 or 1.3v. each function has a monitor bit. i.e. the pon bit is for the power-on reset circuit, and xst bit is for the oscillation halt sensing circuit, and vdet is for the suppl y voltage monitoring circuit. pon and vdet bits are activated to ?h?. however, xst bit is activated to ?l?. the pon and vdet accept only the writing of 0, but xst accepts the writing of 0 and 1. the pon bit is set to 1, when vdd power-up from 0v, but vdet is set to 0, and xst is indefinite. the functions of these three monitor bits are shown in the table below. pon x st vdet function monitoring for the power-on reset function monitoring for the oscillation halt sensing function a drop in supply voltage below a threshold voltage of 2.1 or 1.3v address d4 in address fh d5 in address fh d6 in address fh activated high low high when vdd power up from 0v 1 indefinite 0 accept the writing 0 only both 0 and 1 0 only the relationship between the pon, xst , and vdet is shown in the table below. pon xst vdet conditions of supply voltage and oscillation condition of oscillator, and back-up status 0 0 0 halt on oscillation, but no drop in vdd supply voltage below threshold voltage halt on oscillation cause of condensation etc. 0 0 1 halt on oscillation and drop in vdd supply voltage below threshold voltage, but no drop to 0v halt on oscillation cause of drop in back-up battery voltage 0 1 0 no drop in vdd supply voltage below threshold voltage and no halt in oscillation normal condition 0 1 1 drop in vdd supply voltage below threshold voltage and no halt on oscillation no halt on oscillation, but drop in back-up battery voltage 1 * * drop in supply voltage to 0v power-up from 0v,
r2045s/d 32 32768hz oscillation power-on reset flag (pon) oscillation halt sensin g fla g ( xst ) threshold voltage (2.1v or 1.3v) vdd vdd supply voltage monitor flag (vdet) internal initialization period (1 to 2 sec.) vdet 0 xst 1 pon 0 vdet 0 xst 1 pon 1 vdet 0 xst 1 pon 0 internal initialization period (1 to 2 sec.) when the pon bit is set to 1 in the control register 2, the dev, f6 to f0, wale, dale, 12 /24, clen2 , test, ct2, ct1, ct0, vdsl, vdet, clen1 , ctfg, wafg, and dafg bits are reset to 0 in the oscillation adjustment register, the control register 1, and the control register 2. the pon bit is also set to 1 at power-on from 0 volts. < considerations in using osc illation halt sensing circuit > be sure to prevent the oscillation halt sensing circuit from malfuncti oning by preventing the following: 1) instantaneous power-down on the vdd 2) applying to individual pins voltage exceeding their respective maximum ratings in particular, note that the xst bit may fail to be set to 0 in the presence of any applied supply voltage as illustrated below in such events as backup battery installation. further , give special consid erations to prevent excessive chattering in the oscillation halt sensing circuit. vdd
r2045s/d 33 ? voltage monitoring circuit the vdd supply voltage monitoring circuit is configured to conduct a sampling operation during an interval of 7.8ms per second to check for a drop in supply voltage below a threshold voltage of 2.1 or 1.3v for the vdsl bit setting of 0 (the default setting) or 1, respectively, in t he control register 2, thus minimizing supply current requirements as illustrated in the timing chart below. this circuit suspends a sampling operation once the vdet bit is set to 1 in the control register 2. t he vdd supply voltage monitor is useful for back-up battery checking. vdet ( d6 in address fh ) pon vdd 2.1v or 1.3v 1s vdet 0 7.8ms sampling timing fo r vdd supply voltage internal nitiali-zation period ( 1 to 2sec. ) pon 0 vdet 0
r2045s/d 34 alarm and periodic interrupt the r2045s/d incorporates the alarm interrupt circuit and the periodic interrupt circuit that are configured to generate alarm signals and periodic interrupt signals, respectively, for output from the intr pin as described below. (1) alarm interrupt circuit the alarm interrupt circuit is configured to generate alarm signals for output from the intr , which is driven low (enabled) upon the occurrence of a match between curr ent time read by the time counters (the day-of-week, hour, and minute counters) and alarm time preset by the alarm registers (the alarm_w registers intended for the day-of-week, hour, and minute digit settings and the alar m_d registers intended for the hour and minute digit settings). both the alarm_w and alarm_d are output from the intr . (2) periodic interrupt circuit the periodic interrupt circuit is configured to generate ei ther clock pulses in the pulse mode or interrupt signals in the level mode for output from the intr pin depending on the ct2, ct1, and ct0 bit settings in the control register 1. the above two types of interrupt signals are monitored by the flag bits (i.e. the wafg, dafg, and ctfg bits in the control register 2) and enabled or disabled by t he enable bits (i.e. the wale, dale, ct2, ct1, and ct0 bits in the control register 1) as listed in the table below. flag bits enable bits alarm_w wafg (d1 at address fh) wale (d7 at address eh) alarm_d dafg (d0 at address fh) dale (d6 at address eh) peridic interrupt ctfg (d2 at address fh) ct2=ct1=ct0=0 (these bit setting of ?0? disable the periodic interrupt) (d2 to d0 at address eh) * at power-on, when the wale, dale, ct2, ct1, and ct0 bits are set to 0 in the control register 1, the intr pin is driven high (disabled). * when two types of interrupt signal s are output simultaneously from the intr pin, the output from the intr pin becomes an or waveform of their negative logic. example: combined output to intr pin under control of alarm_d and periodic interrupt periodic interrupt intr alarm_d in this event, which type of interrupt signal is output from the intr pin can be confirmed by reading the dafg, and ctfg bit settings in the control register 2.
r2045s/d 35 ? alarm interrupt the alarm interrupt circuit is controlled by the enable bits (i.e. the wale and dale bits in the control register 1) and the flag bits (i.e. the wafg and dafg bits in the control register 2). the enable bits can be used to enable this circuit when set to 1 and to disable it when set to 0. when intended for reading, the flag bits can be used to monitor alarm interrupt signals. when intended fo r writing, the flag bits will cause no event when set to 1 and will drive high (disable) the alarm interrupt circuit when set to 0. the enable bits will not be affected even when the flag bits are set to 0. in this event, therefore, the alarm interrupt circuit will continue to func tion until it is driven low (enabled ) upon the next occu rrence of a match between current time and preset alarm time. the alarm function can be set by presetting desired alar m time in the alarm regist ers (the alarm_w registers for the day-of-week digit settings and both the alarm_ w registers and the alarm_d registers for the hour and minute digit settings) with the wale and dale bits once se t to 0 and then to 1 in the control register 1. note that the wale and dale bits should be once set to 0 in order to disable the alarm interrupt circuit upon the coincidental occurrence of a match between current ti me and preset alarm time in the process of setting the alarm function. current time = preset alarm time wale 1 (dale) interval (1min.) during which a match between current time and preset alarm time occurs current time = preset alarm time wafg 1 (dale) current time = preset alarm time wale
r2045s/d 36 ? periodic interrupt setting of the periodic selection bits (ct2 to ct0) enables periodic interrupt to the cpu. there are two waveform modes: pulse mode and level mode. in the pulse mode, the output has a waveform duty cycle of around 50%. in the level mode, the output is cyclically driven low and, when the ctfg bit is set to 0, the output is return to high (off). description ct2 ct1 ct0 wave form mode interrupt cycle and falling timing 0 0 0 - off(h) (default) 0 0 1 - fixed at ?l? 0 1 0 pulse mode *1) 2hz(duty50%) 0 1 1 pulse mode *1) 1hz(duty50%) 1 0 0 level mode *2) once per 1 second (synchronized with second counter increment) 1 0 1 level mode *2) once per 1 minute (at 00 seconds of every minute) 1 1 0 level mode *2) once per hour (at 00 minutes and 00 seconds of every hour) 1 1 1 level mode *2) once per month (at 00 hours, 00 minutes, and 00 seconds of first day of every month) *1) pulse mode: 2-hz and 1-hz clock pulses are output in synchronization with the increment of the second counter as illustrated in the timing chart below. intr pin rewriting of the second counter ctfg bit a pprox. 92 s (increment of second counter) in the pulse mode, the increment of the second counter is delayed by approximately 92 s from the falling edge of clock pulses. consequently, time readings immediately after the falling edge of clock pulses may appear to lag behind the time counts of the real-time clocks by approximately 1 second. rewriting the second counter will reset the other time counters of less than 1 second, driving the intr pin low. *2) level mode: periodic interrupt signals are output wi th selectable interrupt cycle settings of 1 second, 1 minute, 1 hour, and 1 month. the in crement of the second counter is sy nchronized with the falling edge of periodic interrupt signals. for example, periodic interrupt signals with an interrupt cycle setting of 1 second are output in synchronization with the increment of the second counter as illustrated in the timing chart below.
r2045s/d 37 ctfg bit intr pin setting ctfg bit to 0 setting ctfg bit to 0 (increment of second counter) (increment of second counter) (increment of second counter) *1), *2) when the oscillation adjustment circuit is us ed, the interrupt cycle will fluctuate once per 20sec. as follows: pulse mode: the ?l? period of output pulses will in crement or decrement by a maximum of 3.784ms. for example, 1-hz clock pulses will have a duty cycle of 50 0.3784%. level mode: a periodic interrupt cycle of 1 second will increment or decrement by a maximum of 3.784 ms. 32-khz clock output for the r2045s/d, 32.768-khz clock pulses are output from the 32kout pin when clen1 or clen2 bit is set to low. if clen1 and clen2 are set to high, the 32kout pin is high impedance. clen1 bit (d3 at address fh) clen2 bit (d4 at address eh) 32kout output pin (n-channel open drain output) 1 1 off(h) 0(default) * * 0(default) 32khz clock output the 32kout pin output is synchronized with the clen1 and clen2 bit settings as illustrated in the timing chart below. 32kout pin max.62.0 s clen1or2 max.45.8 s
r2045s/d 38 typical applications ? typical power circuit configurations sample circuit configuration 1 vdd vss system power supply *1) sample circuit configuration 2 *1) vss system power supply vdd primary battery *1) vss system power supply vdd secondary battery *1) install bypass capacitors for high frequency and low frequency applications in parallel in close vicinity to the r2045s/d. *1) when using an or diode as a power supply for the r2045s/d ensure that voltage exceeding the absolute maximum rating of vdd+0.3v is no t applied the so pin.
r2045s/d 39 ? connection of intr pin the intr pin follows the n-channel open drain output logic and contains no protective diode on the power supply side. as such, it can be connected to a pull-up re sistor of up to 5.5 volts regardless of supply voltage. vdd intr *1) b a backup power supply system power supply vss ? connection of 32kout pin the 32kout pin follows the nch. open drain output and contains no protective diode on the power supply side. as such, it can be connected to a device with a supply voltage of up to 5.5 volts regardless of supply voltage, provided that such connection involves consider ations for the supply current requirements of a pull-up resistor, which can be roughly calc ulated by the following equation: i = 0.5 (v dd or v cc ) / rp vdd 32kout *1) b a backup power supply system power supply vss *1) depending on whether the intr pin is to be used during battery backup, it should be connected to a pull-up resistor at the following different positions: (1) position a in the left diagram when it is not to be used during battery backup. (2) position b in the left diagram when it is to be used during battery backup. *1) depending on whether the 32kout pin is to be used during battery backup, it should be connected to a pull-up resistor at the following different positions: (1) position a in the left diagram when it is no t to be used during battery backup. (2) position b in the left diagram when it is to be used during battery backup.
r2045s/d 40 ? connection of ce pin connection of the ce pin requires the following considerations: 1) the ce pin is configured to enable the oscillation hal t sensing circuit only when driven low. as such, it should be driven low or open at power-on from 0 volts. 2) the ce pin should also be driven low or open immediately upon the host going down (see p.26 "considerations in reading and writing time data under special condition"). i/o control so sclk ce si ce min.0 s vdd lower limit operating voltage for the cpu min.0 smin.0 s 0.2 v dd backup power supply ? connection with 3-wire serial interface bus to connect the r2045s/d with 3-wire serial interface bus, shorten the si and so pins and connect them to the data line as shown in the figure below. ce the other peripheral ic ce1 scl k dat a host sclk sio so ce0 ce sclk si r2045s/d
r2045s/d 41 typical characteristics test circuit frequency counter vdd 32kout vss cl timekeeping current vs. supply voltage timekeeping current vs. supply voltage (with no 32-khz clock output) (witj 32-khz clock output) (output=open, topt=25 c) (output=open, topt=25 c) 0 0.2 0.4 0.6 0.8 1 1.2 0123456 supply voltage vdd(v) timekeeping current idd(ua) 0 0.2 0.4 0.6 0.8 1 1.2 0123456 supply voltage vdd(v) timekeeping current idd(ua) cpu access current vs. scl clock frequen cy timekeeping current vs. operating temperature (output=open, topt=25 c) (output=open, v dd =3v) (wiithout pull-up resister current) 0 10 20 30 40 0 200 400 600 800 1000 scl clock frequency (khz) cpu access current idd(ua) 0 0.2 0.4 0.6 0.8 1 -60 -40 -20 0 20 40 60 80 100 operating temperature topt(celsius) timekeeping current idd(ua) v dd =5v v dd =3v topt : 25 c output : open 32kout output no 32kout output
r2045s/d 42 oscillation frequency deviation vs. supply volt age oscillation frequency deviation vs. (topt=25 c) operating temperature (v dd =3v) -5 -4 -3 -2 -1 0 1 2 3 4 5 0123456 power supply vdd (v) oscillation frequency deviation (ppm) -120 -100 -80 -60 -40 -20 0 20 -60 -40 -20 0 20 40 60 80 100 operating temperature topt(celsius) oscillation frequency deviation (ppm) v ol vs. i ol ( intr pin) v ol vs. i ol ( intr pin) (topt=25 c) (v in =v dd ,topt=25 c) 0 5 10 15 20 25 30 35 00.20.40.60.81 vol (v) iol (ma) 0 5 10 15 20 25 30 35 00.20.40.60.81 vol (v) iol (ma) oscillation start time vs. power supply (topt=25 c) 0 100 200 300 400 500 0123456 power supply vdd (v) oscillation start time (ms) v dd =5v v dd =3v
r2045s/d 43 typical software-based operations ? initialization at power-on start *1) yes no vd et=0 ? warning back-up battery run-down set control register 1 and 2, etc. power-on *2) *4) *3) pon=1? yes no *1) after power-on from 0 volt, the start of oscillation and the process of internal initialization require a time span on the order of 1 to 2sec, so that access should be done after the lapse of this time span or more. *2) the pon bit setting of 0 in the control register 1 indicates power-on from backup battery and not from 0v. for further details, see "p.31 power-on reset, oscillation halt sensing, and supply voltage monitoring ? pon, xst , and vdet ". *3) this step is not required when the supply voltage monitoring circuit is not used. *4) this step involves ordinary initialization including t he oscillation adjustment r egister and interrupt cycle settings, etc.
r2045s/d 44 ? writing of time and calendar data write to time counter and calendar counter *2) ce l *1) ce h *1) write to clock adjustment register *3) ? reading time and calendar data (1) ordinary process of readi ng time and calendar data read from time counter and calendar counter *1) ce l ce h *1) *1) when writing to clock and calendar counters, do not drive ce to l until all times from second to year have been written to prevent error in writing time. for more detailed in "p.25 considerations in reading and writing time data under special condition". *2) any writing to the second counter will reset divider units lower than the second digits. *3) please see ?p,27 the necessity for correction of time count deviations? the r2045s/d may also be initialized not at power-on but in the process of writing time and calendar data. *1) when reading clock and calendar counters, do not drive ce to l until all times from second to year have been written to prevent error in writing time. for more detailed in "p.25 considerations in reading and writing time data under special condition".
r2045s/d 45 (2) basic process of reading time and calendar data with periodic interrupt function *2) other interrupt processes set periodic interrupt cycle selection bits ctfg=1? read from time counter and calendar counter yes no control register 2 (x1x1x011) generate interrupt in cpu *1) *3) *1) this step is intended to select the level mode as a waveform mode for the periodic interrupt function. *2) this step must be completed within 1.0 second. *3) this step is intended to set the ctfg bit to 0 in the control register 2 to cancel an interrupt to the cpu.
r2045s/d 46 (3) applied process of reading time and calendar data with periodic interrupt function time data need not be read from all the time counter s when used for such ordinary purposes as time count indication. this applied process can be used to read time and calendar data with substantial reductions in the load involved in such reading. for time indication in "day-of-month, day-of -week, hour, minute, and second" format: *2) other interrupts processes control register 1 (xxxx0 1 0 0 ) control register 2 (x1x1x011) sec.=00? yes no use previous min.,hr., day,and day-of-week data generate interrupt to cpu *1) *3) ctfg=1? control register 2 (x1x1x011) yes read min.,hr.,day, and day-of-week *4) no *1) this step is intended to select the level mode as a waveform mode fo r the periodic interrupt function. *2) this step must be completed within 1.0 sec. *3) this step is intended to read time data from all the time counters only in the first session of reading time data after writing time data. *4) this step is intended to set the ctfg bit to 0 in the control register 2 to cancel an interrupt to the cpu.
r2045s/d 47 ? interrupt process (1) periodic interrupt *2) other interrupt processes set periodic interrupt cycle selection bits ctfg=1? conduct periodic interrupt yes no control register 2 (x1x1x011) generate interrupt to cpu *1) *1) this step is intended to select the level mode as a waveform mode for the periodic interrupt function. *2) this step is intended to set the ctfg bit to 0 in the control register 2 to cancel an interrupt to the cpu.
r2045s/d 48 (2) alarm interrupt *3) other interrupt processes set alarm min., hr., and day-of-week registers wa fg or da fg=1? conduct alarm interrupt yes no control register 2 (x1x1x101) generate interrupt to cpu *1) wale or dale 1 wale or dale 0 *2) *1) this step is intended to once disable the alarm interrupt circuit by setting the wale or dale bits to 0 in anticipation of the coincidental occurrence of a match between current time and preset alarm time in the process of setting the alarm interrupt function. *2) this step is intended to enable the alarm interrup t function after completion of all alarm interrupt settings. *3) this step is intended to once cancel the alarm interrupt function by writing the settings of "x,1,x, 1,x,1,0,1" and "x,1,x,1,x,1,1,0" to the alarm_w registers and the alarm_d registers, respectively.
r2045s/d 49 land pattern (reference) ? r2045s (sop14) 8 0.7 1.27 1 7 8.32 p 1.27x6=7.62 14 5.4 1.4 1.4 unit:mm package top view 14 1 7 8 1. pad layout and size can modify by customers material, equipment, and method. please adjust pad layout according to your conditions. 2. in the mount area which descried as , is close to the inside oscillator circuit. to avoid the malfunction b y noise, check the other signal lines close to the area, do not intervene with the oscillator circuit. 3. a part of a metal case of the crystal may be seen in the area which described as in both sides of the package. it has no influence on the characteristics and quality of the product.
r2045s/d 50 ? R2045D (son22) 0.7 14 0.25 0.5 1 11 0.7 5.25 p 0.5x10=5.0 0.8 0.8 1.4 0.25 0.75 22 4.0 0.7 0.7 unit : mm package top view package bottom view 22 11 1 14 22 14 1 11 1. pad layout and size can modify by customers material, equipment, and method. please adjust pad layout according to your conditions. 2. any signal line should not pass through the area that described as in the land pattern. if a signal line is located in that area, it may cause a short circuit with a tab suspension leads which is marked with in the figure above or unnecessary remainder of cut lead. 3. in the mount area which descried as , is close to the inside oscillator circuit. to avoid the malfunction by noise, check the other signal lines close to the area, do not intervene with the oscillator circuit. 4. a part of a metal case of the crystal may be seen in the area that described as in both sides of the package. it has no influence on the characteristics and quality of the product.

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